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發現，原來VHDL好好玩..XD
貼上一個可能會錯的程式碼，今天要把實驗做到有趣極了為止，晚點再po上簡化程式碼

library ieee;
use ieee.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use IEEE.std_logic_unsigned.all;

entity fulladder7 is port(integer1,integer2: in std_logic_vector(3 downto 0);
                          i1,i2,s1,s2:out std_logic_vector(0 to 6));
end fulladder7;
architecture a of fulladder7 is
       signal temp_sum, temp_sub: std_logic_vector(4 downto 0);
       signal temp_sum2:std_logic_vector(3 downto 0);
begin
    process(integer1)
 begin
  case integer1 is
  when "0000"=> i1 <="1111110";
  when "0001"=> i1 <="0110000";
  when "0010"=> i1 <="1101101";
  when "0011"=> i1 <="1111001";
  when "0100"=> i1 <="0110011";
  when "0101"=> i1 <="1011011";
  when "0110"=> i1 <="1011111";
  when "0111"=> i1 <="1110010";
  when "1000"=> i1 <="1111111";
  when "1001"=> i1 <="1111011";
  when others=> i1 <="0000000";
     end case;
     end process;

    process(integer2)
 begin
  case integer2 is
  when "0000"=> i2 <="1111110";
  when "0001"=> i2 <="0110000";
  when "0010"=> i2 <="1101101";
  when "0011"=> i2 <="1111001";
  when "0100"=> i2 <="0110011";
  when "0101"=> i2 <="1011011";
  when "0110"=> i2 <="1011111";
  when "0111"=> i2 <="1110010";
  when "1000"=> i2 <="1111111";
  when "1001"=> i2 <="1111011";
  when others=> i2 <="0000000";
     end case;
     end process; 
    
     process(integer1, integer2)
     begin
         temp_sum <= integer1 + integer2;
         
         if temp_sum >= "01010" then
            temp_sub <= temp_sum - "01010";        
            temp_sum2 <= "0001";
         else
            temp_sub <= temp_sum;
            temp_sum2 <= "0000";
         end if;

     end process;
    
     
     process(temp_sub)
  begin
    case temp_sub is
    when "00000" => s1 <= "1111110";
   when "00001" => s1 <= "0110000";
  when "00010" => s1 <= "1101101";
  when "00011" => s1 <= "1111001";
  when "00100" => s1 <= "0110011";
  when "00101" => s1 <= "1011011";
  when "00110" => s1 <= "1011111";
  when "00111" => s1 <= "1110010";
  when "01000" => s1 <= "1111111";
  when "01001" => s1 <= "1111011";
  when others => s1 <= "0000000";
     end case;
     end process;

     process(temp_sum2)
      begin
          case temp_sum2 is
          when "0000" => s2 <= "1111110";
        when "0001" => s2 <= "0110000";
       when others => s2 <= "0000000";
        end case;
     end process;
end  a;

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事實上現在就可以開始著手進行簡化工作了